Virtex-4 clocking

M

Melanie Nasic

Guest
Hi fellow engineers,

I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some
experience in board design and have already used several Virtex and
Virtex-II devices. I want an ICS8442 LVDS clock synthesizer to be the clock
source of my Virtex-4.
A look at the Virtex-4 User Guide (ug070.pdf) scared me a lot by stating
"Clock inputs can be configured for any I/O standard, including differential
I/O standards. Each clock input can be either single-ended or differential.
All 16 or 32 clock inputs can be differential if desired. Global clock
inputs can be configured for any I/O standard except LVDS and HT output
differential standards. Only CSE output differential standards are supported
by the global clock input pins."
Does that mean that I am not allowed to connect an LVDS clock to the
Global-clock inputs? Or did I get something wrong here? I have to use the
ICS8442 because of the large frequency scale from 25-700 MHz.

Regards, Melanie
 
"Melanie Nasic" <quinn_the_esquimo@freenet.de> schrieb im Newsbeitrag
news:do8vhr$sv9$1@mamenchi.zrz.TU-Berlin.DE...
Hi fellow engineers,

I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some
experience in board design and have already used several Virtex and
Virtex-II devices. I want an ICS8442 LVDS clock synthesizer to be the
clock source of my Virtex-4.
A look at the Virtex-4 User Guide (ug070.pdf) scared me a lot by stating
"Clock inputs can be configured for any I/O standard, including
differential I/O standards. Each clock input can be either single-ended or
differential. All 16 or 32 clock inputs can be differential if desired.
Global clock inputs can be configured for any I/O standard except LVDS and
HT output differential standards. Only CSE output differential standards
are supported by the global clock input pins."
Does that mean that I am not allowed to connect an LVDS clock to the
Global-clock inputs? Or did I get something wrong here? I have to use the
ICS8442 because of the large frequency scale from 25-700 MHz.

Regards, Melanie

no nothing wrong, read it once more time
Click to expand...

the clock input pins can not be used LVDS OUTPUT
they of course can be used as LVDS input.

the restriction of some V4 lvds iopins of being input only for LVDS is new
it is related to the 'low capacitance' of those pins I think

Antti
 
"Antti Lukats" <antti@openchip.org> wrote in message
news:do8vsi$22q$03$1@news.t-online.com...
"Melanie Nasic" <quinn_the_esquimo@freenet.de> schrieb im Newsbeitrag
news:do8vhr$sv9$1@mamenchi.zrz.TU-Berlin.DE...
Hi fellow engineers,

I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some
experience in board design and have already used several Virtex and
Virtex-II devices. I want an ICS8442 LVDS clock synthesizer to be the
clock source of my Virtex-4.
A look at the Virtex-4 User Guide (ug070.pdf) scared me a lot by stating
"Clock inputs can be configured for any I/O standard, including
differential I/O standards. Each clock input can be either single-ended
or differential. All 16 or 32 clock inputs can be differential if
desired. Global clock inputs can be configured for any I/O standard
except LVDS and HT output differential standards. Only CSE output
differential standards are supported by the global clock input pins."
Does that mean that I am not allowed to connect an LVDS clock to the
Global-clock inputs? Or did I get something wrong here? I have to use the
ICS8442 because of the large frequency scale from 25-700 MHz.

Regards, Melanie

no nothing wrong, read it once more time

the clock input pins can not be used LVDS OUTPUT
they of course can be used as LVDS input.

the restriction of some V4 lvds iopins of being input only for LVDS is new
it is related to the 'low capacitance' of those pins I think

Antti
Click to expand...
Antti is correct, but I, too, was confused by the wording in the user guide.
I contacted our FAE and he confirmed that the restriction is only when using
these pins as outputs.

Bob
 
Antti,

Yes, some pins do not have the LVDS output structure. The "low
capacitance" that affords is a mere 0.5 pF, so I think more appropriate
would be to say these pins just don't have these two IO output standards
available to them.

Austin

Antti Lukats wrote:

"Melanie Nasic" <quinn_the_esquimo@freenet.de> schrieb im Newsbeitrag
news:do8vhr$sv9$1@mamenchi.zrz.TU-Berlin.DE...

Hi fellow engineers,

I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some
experience in board design and have already used several Virtex and
Virtex-II devices. I want an ICS8442 LVDS clock synthesizer to be the
clock source of my Virtex-4.
A look at the Virtex-4 User Guide (ug070.pdf) scared me a lot by stating
"Clock inputs can be configured for any I/O standard, including
differential I/O standards. Each clock input can be either single-ended or
differential. All 16 or 32 clock inputs can be differential if desired.
Global clock inputs can be configured for any I/O standard except LVDS and
HT output differential standards. Only CSE output differential standards
are supported by the global clock input pins."
Does that mean that I am not allowed to connect an LVDS clock to the
Global-clock inputs? Or did I get something wrong here? I have to use the
ICS8442 because of the large frequency scale from 25-700 MHz.

Regards, Melanie


no nothing wrong, read it once more time

the clock input pins can not be used LVDS OUTPUT
they of course can be used as LVDS input.

the restriction of some V4 lvds iopins of being input only for LVDS is new
it is related to the 'low capacitance' of those pins I think

Antti
Click to expand...
 
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:do988l$84u2@xco-news.xilinx.com...
Antti,

Yes, some pins do not have the LVDS output structure. The "low
capacitance" that affords is a mere 0.5 pF, so I think more appropriate
would be to say these pins just don't have these two IO output standards
available to them.

Austin

Hi Austin
Click to expand...

yes I know, I learned it the hard way, I was jump starting a FX12 board
with LVDS _output_ clock connected in the banks that do not LVDS
out (eg banks 0..3 for FX12-SF363) - after reading the datasheet, well
its all in the datasheet but I guess there are more people around
to find this issue the hard way.

Antti
 
I totally agree on that, Antti! The information given in the user guide is
very misleading.


"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:do998g$nc3$00$1@news.t-online.com...
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:do988l$84u2@xco-news.xilinx.com...
Antti,

Yes, some pins do not have the LVDS output structure. The "low
capacitance" that affords is a mere 0.5 pF, so I think more appropriate
would be to say these pins just don't have these two IO output standards
available to them.

Austin

Hi Austin

yes I know, I learned it the hard way, I was jump starting a FX12 board
with LVDS _output_ clock connected in the banks that do not LVDS
out (eg banks 0..3 for FX12-SF363) - after reading the datasheet, well
its all in the datasheet but I guess there are more people around
to find this issue the hard way.

Antti
Click to expand...
 
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